60 #if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
61 static void ff_weighted_vector_sumf_mips(
62 float *
out,
const float *in_a,
const float *in_b,
63 float weight_coeff_a,
float weight_coeff_b,
int length)
65 const float *a_end = in_a + length;
69 "blez %[length], ff_weighted_vector_sumf_end%= \n\t"
71 "ff_weighted_vector_sumf_madd%=: \n\t"
72 "lwc1 $f0, 0(%[in_a]) \n\t"
73 "lwc1 $f3, 4(%[in_a]) \n\t"
74 "lwc1 $f1, 0(%[in_b]) \n\t"
75 "lwc1 $f4, 4(%[in_b]) \n\t"
76 "mul.s $f2, %[weight_coeff_a], $f0 \n\t"
77 "mul.s $f5, %[weight_coeff_a], $f3 \n\t"
78 "madd.s $f2, $f2, %[weight_coeff_b], $f1 \n\t"
79 "madd.s $f5, $f5, %[weight_coeff_b], $f4 \n\t"
82 "swc1 $f2, 0(%[out]) \n\t"
83 "swc1 $f5, 4(%[out]) \n\t"
85 "bne %[in_a], %[a_end], ff_weighted_vector_sumf_madd%= \n\t"
87 "ff_weighted_vector_sumf_end%=: \n\t"
89 : [
out]
"+r" (
out), [in_a]
"+r" (in_a), [in_b]
"+r" (in_b)
90 : [weight_coeff_a]
"f" (weight_coeff_a),
91 [weight_coeff_b]
"f" (weight_coeff_b),
92 [length]
"r" (length), [a_end]
"r"(a_end)
93 :
"$f0",
"$f1",
"$f2",
"$f3",
"$f4",
"$f5",
"memory"
102 #if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
103 c->weighted_vector_sumf = ff_weighted_vector_sumf_mips;
void ff_acelp_vectors_init_mips(ACELPVContext *c)
MIPS assembly defines from sys/asm.h but rewritten for use with C inline assembly (rather than from w...
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")